Our Technology
Secure the entire package
rather than each silicon chip
The Problem
Security is complex and expensive
Attacks are comparatively easy and cheap
Current Approach
Security features embedded in modern SoCs consume valuable area in advanced-node silicon
Our solution
Introducing the Chip SCIF™
Chip SCIFTM leverages semiconductor advanced packaging to create a secure enclave (i.e. a chip-scale ‘SCIF’). A purpose-built security chiplet handles the security logic, while a mix of active and passive physics-based technologies are built into the package enclosure.
Chip SCIFTM protects against side-channel attacks, reverse engineering, data/IP theft, and fault injections using a combination of electromagnetic elements, PUF-based root of trust, obfuscation techniques, and intrusion detection schemes.
Chip SCIFTM package-level protection complements die-level hardware and cyber security solutions for multi-layered security protections.
Current Approach
Currently, expensive and complex security features are built into each silicon chip (if at all)
Chip SCIF™
Our approach uses a low-cost, purpose-built security chiplet that interfaces with wiring built into the package to secure the entire volume
Reduced cost & complexity
Rapid design &
development
Agile, scalable
manufacturing
Our Advantage
Performance & Differentiation
Chip SCIF™ is a physical, package-level security solution scaling to 200 mm, 300 mm, and panel-level advanced package substrates.
Our technology is applicable to fan out wafer level packaging (FOWLP), interposer-based packages, stacked dies, 3D heterogenous integration (3DHI), and next-generation chiplet system architectures.
Moving system security functions from the silicon to the package enables use of leading-edge COTS components while still meeting stringent security standards.
System engineers can maximize functional capability while security engineers focus on certification, without direct competition for area, compute, power, and thermal budgets.
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Take control of your data security.